Backup Domain Reset; Clocks - ST STM32F423 Reference Manual

RM0430
6.1.3

Backup domain reset

The backup domain reset sets all RTC registers and the RCC_BDCR register to their reset
values.
A backup domain reset is generated when one of the following events occurs:
1. Software reset, triggered by setting the BDRST bit in the
register
2. V
DD
6.2

Clocks

Three different clock sources can be used to drive the system clock (SYSCLK):
•
HSI oscillator clock
•
HSE oscillator clock
•
Main PLL (PLL) clock
The devices have the two following secondary clock sources:
•
32 kHz low-speed internal RC (LSI RC) which drives the independent watchdog and,
optionally, the RTC used for Auto-wakeup from the Stop/Standby mode.
•
32.768 kHz low-speed external crystal (LSE crystal) which optionally drives the RTC
clock (RTCCLK)
Each clock source can be switched on or off independently when it is not used, to optimize
power consumption.
(RCC_BDCR).
or V power on, if both supplies have previously been powered off.
BAT
Reset and clock control (RCC) for STM32F413/423
RM0430 Rev 8
RCC Backup domain control
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