ST STM32F423 Reference Manual page 896

Advanced arm-based 32-bit mcus
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Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit-
Framing error
A framing error is detected when:
The stop bit is not recognized on reception at the expected time, following either a de-
synchronization or excessive noise.
When the framing error is detected:
The FE bit is set by hardware
The invalid data is transferred from the Shift register to the USART_DR register.
No interrupt is generated in case of single byte communication. However this bit rises
at the same time as the RXNE bit that itself generates an interrupt. In case of
multibuffer communication an interrupt will be issued if the EIE bit is set in the
USART_CR3 register.
The FE bit is reset by a USART_SR register read operation followed by a USART_DR
register read operation.
Configurable stop bits during reception
The number of stop bits to be received can be configured through the control bits of Control
Register 2 - it can be either 1 or 2 in normal mode and 0.5 or 1.5 in Smartcard mode.
1.
0.5 stop bit (reception in Smartcard mode): No sampling is done for 0.5 stop bit. As
a consequence, no framing error and no break frame can be detected when 0.5 stop bit
is selected.
2.
1 stop bit: Sampling for 1 stop Bit is done on the 8
3.
1.5 stop bits (Smartcard mode): When transmitting in smartcard mode, the device
must check that the data is correctly sent. Thus the receiver block must be enabled (RE
=1 in the USART_CR1 register) and the stop bit is checked to test if the smartcard has
detected a parity error. In the event of a parity error, the smartcard forces the data
signal low during the sampling - NACK signal-, which is flagged as a framing error.
Then, the FE flag is set with the RXNE at the end of the 1.5 stop bit. Sampling for 1.5
stop bits is done on the 16
beginning of the stop bit). The 1.5 stop bit can be decomposed into two parts: one 0.5
baud clock period during which nothing happens, followed by 1 normal stop bit period
during which sampling occurs halfway through. Refer to
details.
4.
2 stop bits: Sampling for 2 stop bits is done on the 8
stop bit. If a framing error is detected during the first stop bit the framing error flag will
896/1324
Table 158. Noise detection from sampled data (continued)
Sampled value
010
011
100
101
110
111
th
NE status
1
1
1
1
1
0
th
th
, 17
and 18
samples (1 baud clock period after the
RM0430 Rev 8
Received bit value
0
1
0
1
1
1
th
th
th
, 9
and 10
samples.
Section 28.4.11
th
th
th
, 9
and 10
samples of the first
for more

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