Serial Channel Transceivers - ST STM32F423 Reference Manual

Digital filter for sigma delta modulators (DFSDM)
DFSDM clocks
The internal DFSDM clock f
digital processing blocks (digital filter, integrator) and next additional blocks (analog
watchdog, short-circuit detector, extremes detector, control block) is generated by the RCC
block and is derived from the system clock SYSCLK or peripheral clock PCLK2 (see
DFSDMSEL bit description in ). The DFSDM clock is automatically stopped in stop mode (if
DFEN = 0 for all DFSDM_FLTx, x=0..3).
The DFSDM serial channel transceivers can receive an external serial clock to sample an
external serial data stream. The internal DFSDM clock must be at least 4 times faster than
the external serial clock if standard SPI coding is used, and 6 times faster than the external
serial clock if Manchester coding is used.
DFSDM can provide one external output clock signal to drive external Σ∆ modulator(s) clock
input(s). It is provided on CKOUT pin. This output clock signal must be in the range
specified in given device datasheet and is derived from DFSDM clock or from audio clock
(see CKOUTSRC bit in DFSDM_CH0CFGR1 register) by programmable divider in the
range 2 - 256 (CKOUTDIV in DFSDM_CH0CFGR1 register). Audio clock source is SAI1
clock selected by SAI1SEL[1:0] field in RCC configuration (see ).
15.4.4

Serial channel transceivers

There are 8 multiplexed serial data channels which can be selected for conversion by each
filter or Analog watchdog or Short-circuit detector. Those serial transceivers receive data
stream from external Σ∆ modulator. Data stream can be sent in SPI format or Manchester
coded format (see SITP[1:0] bits in DFSDM_CHyCFGR1 register).
The channel is enabled for operation by setting CHEN=1 in DFSDM_CHyCFGR1 register.
Channel inputs selection
Serial inputs (data and clock signals) from DATINy and CKINy pins can be redirected from
the following channel pins. This serial input channel redirection is set by CHINSEL bit in
DFSDM_CHyCFGR1 register.
Channel redirection can be used to collect audio data from PDM (pulse density modulation)
stereo microphone type. PDM stereo microphone has one data and one clock signal. Data
signal provides information for both left and right audio channel (rising clock edge samples
for left channel and falling clock edge samples for right channel).
Configuration of serial channels for PDM microphone input:
•
PDM microphone signals (data, clock) will be connected to DFSDM input serial channel
y (DATINy, CKOUT) pins.
• Channel y will be configured: CHINSEL = 0 (input from given channel pins: DATINy,
CKINy).
•
Channel (y-1) (modulo 8) will be configured: CHINSEL = 1 (input from the following
channel ((y-1)+1) pins: DATINy, CKINy).
•
Channel y: SITP[1:0] = 0 (rising edge to strobe data) => left audio channel on channel
y.
• Channel (y-1): SITP[1:0] = 1 (falling edge to strobe data) => right audio channel on
channel y-1.
•
Two DFSDM filters will be assigned to channel y and channel (y-1) (to filter left and
right channels from PDM microphone).
394/1324
, which is used to drive the channel transceivers,
DFSDMCLK
RM0430 Rev 8
RM0430