Debug Mode; Fmpi2C Low-Power Modes; Table 150. Low-Power Modes - ST STM32F423 Reference Manual

Fast-mode Plus Inter-integrated circuit (FMPI2C) interface
NBYTES counter. Refer to
•
In slave mode:
–
–
•
For instances supporting SMBus: the PEC transfer is managed with NBYTES counter.
Refer to
page
Note: If DMA is used for transmission, the TXIE bit does not need to be enabled.
Reception using DMA
DMA (Direct Memory Access) can be enabled for reception by setting the RXDMAEN bit in
the FMPI2C_CR1 register. Data is loaded from the FMPI2C_RXDR register to an SRAM
area configured using the DMA peripheral (refer to ) whenever the RXNE bit is set. Only the
data (including PEC) are transferred with DMA.
•
In master mode, the initialization, the slave address, direction, number of bytes and
START bit are programmed by software. When all data are transferred using DMA, the
DMA must be initialized before setting the START bit. The end of transfer is managed
with the NBYTES counter.
•
In slave mode with NOSTRETCH=0, when all data are transferred using DMA, the
DMA must be initialized before the address match event, or in the ADDR interrupt
subroutine, before clearing the ADDR flag.
•
If SMBus is supported (see
managed with the NBYTES counter. Refer to
SMBus Master receiver on page
Note: If DMA is used for reception, the RXIE bit does not need to be enabled.
26.4.16

Debug mode

When the microcontroller enters debug mode (core halted), the SMBus timeout either
continues to work normally or stops, depending on the DBG_I2Cx_ configuration bits in the
DBG module.
26.5

FMPI2C low-power modes

Mode
Sleep
Stop
Standby The FMPI2C peripheral is powered down and must be reinitialized after exiting Standby.
830/1324
With NOSTRETCH=0, when all data are transferred using DMA, the DMA must be
initialized before the address match event, or in ADDR interrupt subroutine, before
clearing ADDR.
With NOSTRETCH=1, the DMA must be initialized before the address match
event.
SMBus Slave transmitter on page 820
824.

Table 150. Low-power modes

No effect
FMPI2C interrupts cause the device to exit the Sleep mode.
The contents of FMPI2C registers are kept.
Master transmitter on page
and
Section 26.3: FMPI2C
SMBus Slave receiver on page 822
826.
Description
RM0430 Rev 8
806.
SMBus Master transmitter on
implementation): the PEC transfer is
RM0430
and