Table 68. Fsmc_Bcrx Bit Fields; Figure 50. Synchronous Multiplexed Write Mode Waveforms - Psram (Cram) - ST STM32F423 Reference Manual

RM0430

Figure 50. Synchronous multiplexed write mode waveforms - PSRAM (CRAM)

1. The memory must issue NWAIT signal one cycle in advance, accordingly WAITCFG must be programmed to 0.
2. Byte Lane (NBL) outputs are not shown, they are held low while NEx is active.
Bit number
31:22
21
20
19
18:16
15
14
13

Table 68. FSMC_BCRx bit fields

Bit name
Reserved 0x000
WFDIS As needed
CCLKEN As needed
CBURSTRW 0x1
CPSIZE As needed (0x1 for CRAM 1.5)
ASYNCWAIT 0x0
EXTMOD 0x0
To be set to 1 if the memory supports this feature, to be kept at 0
WAITEN
otherwise.
RM0430 Rev 8
Flexible static memory controller (FSMC)
Value to set
295/1324
306