Own Address 1 Register (Fmpi2C_Oar1) - ST STM32F423 Reference Manual

RM0430
26.7.3

Own address 1 register (FMPI2C_OAR1)

Address offset: 0x08
Reset value: 0x0000 0000
Access: No wait states, except if a write access occurs while a write access to this register is
ongoing. In this case, wait states are inserted in the second write access until the previous
one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x
FMPI2CCLK.
31 30 29
Res. Res. Res. Res.
15 14 13
OA1EN Res. Res. Res.
rw
Bits 31:16 Reserved, must be kept at reset value.
Bit 15 OA1EN: Own Address 1 enable
0: Own address 1 disabled. The received slave address OA1 is NACKed.
1: Own address 1 enabled. The received slave address OA1 is ACKed.
Bits 14:11 Reserved, must be kept at reset value.
Bit 10 OA1MODE: Own Address 1 10-bit mode
0: Own address 1 is a 7-bit address.
1: Own address 1 is a 10-bit address.
Note: This bit can be written only when OA1EN=0.
Bits 9:8 OA1[9:8]: Interface address
7-bit addressing mode: do not care
10-bit addressing mode: bits 9:8 of address
Note: These bits can be written only when OA1EN=0.
Bits 7:1 OA1[7:1]: Interface address
7-bit addressing mode: 7-bit address
10-bit addressing mode: bits 7:1 of 10-bit address
Note: These bits can be written only when OA1EN=0.
Bit 0 OA1[0]: Interface address
7-bit addressing mode: do not care
10-bit addressing mode: bit 0 of address
Note: This bit can be written only when OA1EN=0.
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface
28 27 26 25
Res. Res. Res.
12 11 10 9
OA1
Res. OA1[9:8]
MODE
rw rw
24 23 22
Res. Res. Res.
8 7 6
rw rw rw
RM0430 Rev 8
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
OA1[7:1]
rw rw rw rw
17 16
Res. Res.
1 0
OA1[0]
rw rw
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