Dfsdm Filter X Extremes Detector Minimum Register; (Dfsdm_Fltxexmin); Dfsdm Filter X Conversion Timer Register (Dfsdm_Fltxcnvtimr) - ST STM32F423 Reference Manual

RM0430
15.8.14

DFSDM filter x extremes detector minimum register

(DFSDM_FLTxEXMIN)

Address offset: 0x134 + 0x80 * x, (x = 0 to 3)
Reset value: 0x7FFF FF00
31 30 29
rc_r rs_r rs_r
15 14 13
rs_r rs_r rs_r
Bits 31:8 EXMIN[23:0]: Extremes detector minimum value
These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx.
EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register.
Bits 7:3 Reserved, must be kept at reset value.
Bits 2:0 EXMINCH[2:0]: Extremes detector minimum data channel
These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits
are cleared by reading of this register.
15.8.15

DFSDM filter x conversion timer register (DFSDM_FLTxCNVTIMR)

Address offset: 0x138 + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000
31 30 29
r r r
15 14 13
r r r
28 27 26 25
rs_r rs_r rs_r rs_r
12 11 10 9
EXMIN[7:0]
rs_r rs_r rs_r rs_r
28 27 26 25
r r r r
12 11 10 9
CNVCNT[11:0]
r r r r
Digital filter for sigma delta modulators (DFSDM)
24 23 22
EXMIN[23:8]
rs_r rs_r rs_r
8 7 6
Res. Res.
rs_r
24 23 22
CNVCNT[27:12]
r r r
8 7 6
r r r
RM0430 Rev 8
21 20 19 18
rs_r rs_r rs_r rs_r
5 4 3 2
Res. Res. Res.
r
21 20 19 18
r r r r
5 4 3 2
Res. Res.
r r
17 16
rs_r rs_r
1 0
EXMINCH[2:0]
r r
17 16
r r
1 0
Res. Res.
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