Lptim Configuration Register (Lptim_Cfgr) - ST STM32F423 Reference Manual

Low-power timer (LPTIM)
21.6.4

LPTIM configuration register (LPTIM_CFGR)

Address offset: 0x00C
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
TRIGSEL[2:0] Res.
rw rw rw
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 Reserved, must be kept at reset value.
Bits 28:25 Reserved, must be kept at reset value.
Bit 24 ENC: Encoder mode enable
The ENC bit controls the Encoder mode
0: Encoder mode disabled
1: Encoder mode enabled
Bit 23 COUNTMODE: counter mode enabled
The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:
0: the counter is incremented following each internal clock pulse
1: the counter is incremented following each valid clock pulse on the LPTIM external Input1
Bit 22 PRELOAD: Registers update mode
The PRELOAD bit controls the LPTIM_ARR and the LPTIM_CMP registers update modality
0: Registers are updated after each APB bus write access
1: Registers are updated at the end of the current LPTIM period
Bit 21 WAVPOL: Waveform shape polarity
The WAVEPOL bit controls the output polarity
0: The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP
registers
1: The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and
LPTIM_CMP registers
Bit 20 WAVE: Waveform shape
The WAVE bit controls the output shape
0: Deactivate Set-once mode, PWM / One Pulse waveform (depending on OPMODE bit)
1: Activate the Set-once mode
Bit 19 TIMOUT: Timeout enable
The TIMOUT bit controls the Timeout feature
0: a trigger event arriving when the timer is already started will be ignored
1: A trigger event arriving when the timer is already started will reset and restart the counter
670/1324
27 26 25 24
Res. Res. Res. ENC
rw
11 10 9 8
PRESC[2:0] Res.
rw rw rw
23 22 21
COUNT
PRELOAD WAVPOL
MODE
rw rw rw
7 6 5
TRGFLT[1:0] Res.
rw rw
RM0430 Rev 8
20 19 18
WAVE TIMOUT TRIGEN[1:0]
rw rw rw
4 3 2
CKFLT[1:0] CKPOL[1:0]
rw rw rw
RM0430
17 16
Res.
rw
1 0
CKSEL
rw rw