ST STM32F423 Reference Manual page 211

RM0430
Bit 16
Bit 15
Bit14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
DFSDM2_CK37SEL: Distribution of the DFSDM2 bitstream clock gated by TIM3 OC1
(DM3 demultiplexer on Figure 81: Multi-channel delay block for pulse
0: The gated clock is distributed to CkIn3 (DM3 = 0)
1: The gated clock is distributed to CkIn7 (DM3 = 1)
DFSDM2_CK26SEL: Distribution of the DFSDM2 bitstream clock gated by TIM3 OC2
(DM4 demultiplexer on Figure 81: Multi-channel delay block for pulse
0: The gated clock is distributed to CkIn2 (DM4 = 0)
1: The gated clock is distributed to CkIn6 (DM4 = 1)
DFSDM2_CK15SEL: Distribution of the DFSDM2 bitstream clock gated by TIM3 OC3
(DM5 demultiplexer on Figure 81: Multi-channel delay block for pulse
0: The gated clock is distributed to CkIn1 (DM5 = 0)
1: The gated clock is distributed to CkIn5 (DM5 = 1)
DFSDM2_CK04SEL: Distribution of the DFSDM2 bitstream clock gated by TIM3 OC4
(DM6 demultiplexer on Figure 81: Multi-channel delay block for pulse
0: The gated clock is distributed to CkIn0 (DM6 = 0)
1: The gated clock is distributed to CkIn4 (DM6 = 1)
DFSDM2_D6SEL: Source selection for DatIn6 of DFSDM2 (M20 multiplexer on
Figure 81: Multi-channel delay block for pulse
0: The source for DatIn6 is from the DFSDM2_DATIN6 pin (M20 = 0)
1: DatIn6 is sharing the same data than DatIn7 (M20 = 1)
DFSDM2_D4SEL: Source selection for DatIn4 of DFSDM2 (M19 multiplexer on
Figure 81: Multi-channel delay block for pulse
0: The source for DatIn4 is from the DFSDM2_DATIN4 pin (M19 = 0)
1: DatIn4 is sharing the same data than DatIn5 (M19 = 1)
DFSDM2_D2SEL: Source selection for DatIn2 of DFSDM2 (M18 multiplexer on
Figure 81: Multi-channel delay block for pulse
0: The source for DatIn2 is from the DFSDM2_DATIN2 pin (M18 = 0)
1: DatIn2 is sharing the same data than DatIn3 (M18 = 1)
DFSDM2_D0SEL: Source selection for DatIn0 of DFSDM2 (M17 multiplexer on
Figure 81: Multi-channel delay block for pulse
0: The source for DatIn0 is from the DFSDM2_DATIN0 pin (M17 = 0)
1: DatIn0 is sharing the same data than DatIn1 (M17 = 1)
MCHDLYEN2: MCHDLY clock enable for DFSDM2 (G3,G4,G5,G6 gating signal on
Figure 81: Multi-channel delay block for pulse
0: Delay clock for DFSDM2 is disabled (G[6:3] = 0)
1: Delay clock for DFSDM2 is enabled (G[6:3] = 1)
DFSDM1_CKOSEL: Source selection for DFSDM1_CKOUT (M1 multiplexer on
Figure 81: Multi-channel delay block for pulse
0: The source for DFSDM1_CKOUT is the CkOut generated by the DFSDM1 (M1=0)
1: The source for DFSDM1_CKOUT is the output of M27 (M1=1)
DFSDM1_CFG: CkIn source selection for DFSDM1 (M3,M4,M5,M6 multiplexer on
Figure 1)
0: The source for CkIn[3:0] signals are the pins DFSDM1_CKINy (M[6:3] = 0)
1: The source for CkIn[3:0] signals are provided by the outputs of DM[2:1] (M[6:3] = 1)
DFSDM1_CK13SEL: Distribution of the DFSDM1 bitstream clock gated by TIM4 OC1
(DM1 demultiplexer on Figure 81: Multi-channel delay block for pulse
0: The gated clock is distributed to CkIn1 (DM1 = 0)
1: The gated clock is distributed to CkIn3 (DM1 = 1)
RM0430 Rev 8
System configuration controller (SYSCFG)
skipping)
skipping)
skipping)
skipping)
skipping)
skipping)
skipping)
skipping)
skipping)
skipping)
skipping)
211/1324
213