RM0430
26.7.5
Timing register (FMPI2C_TIMINGR)
Address offset: 0x10
Reset value: 0x0000 0000
Access: No wait states
31
30
29
28
PRESC[3:0]
rw
rw
rw
rw
15
14
13
12
SCLH[7:0]
rw
rw
rw
rw
Bits 31:28 PRESC[3:0]: Timing prescaler
This field is used to prescale FMPI2CCLK in order to generate the clock period t
data setup and hold counters (refer to
level counters (refer to
t
PRESC
Bits 27:24 Reserved, must be kept at reset value.
Bits 23:20 SCLDEL[3:0]: Data setup time
This field is used to generate a delay t
master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during
t
SCLDEL
t
SCLDEL
Note: t
Bits 19:16 SDADEL[3:0]: Data hold time
This field is used to generate the delay t
master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during
t
SDADEL
t
SDADEL
Note: SDADEL is used to generate t
Bits 15:8 SCLH[7:0]: SCL high period (master mode)
This field is used to generate the SCL high period in master mode.
t
SCLH
Note: SCLH is also used to generate t
Bits 7:0 SCLL[7:0]: SCL low period (master mode)
This field is used to generate the SCL low period in master mode.
t
SCLL
Note: SCLL is also used to generate t
Note:
This register must be configured when the FMPI2C is disabled (PE = 0).
Note:
The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C
Configuration window.
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface
27
26
25
24
Res.
Res.
Res.
Res.
11
10
9
8
rw
rw
rw
rw
FMPI2C master initialization on page
= (PRESC+1) x t
I2CCLK
.
= (SCLDEL+1) x t
PRESC
is used to generate t
SCLDEL
.
= SDADEL x t
PRESC
= (SCLH+1) x t
PRESC
= (SCLL+1) x t
PRESC
RM0430 Rev 8
23
22
21
20
SCLDEL[3:0]
rw
rw
rw
rw
7
6
5
rw
rw
rw
rw
FMPI2C timings on page
between SDA edge and SCL rising edge. In
SCLDEL
timing.
SU:DAT
between SCL falling edge and SDA edge. In
SDADEL
timing.
HD:DAT
and t
timing.
SU:STO
HD:STA
and t
timings.
BUF
SU:STA
19
18
17
SDADEL[3:0]
rw
rw
rw
4
3
2
1
SCLL[7:0]
rw
rw
rw
PRESC
787) and for SCL high and low
802).
16
rw
0
rw
used for
839/1324
847
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