I2C Slave Mode; Figure 286. I2C Block Diagram - ST STM32F423 Reference Manual

RM0430
The block diagram of the I
1. SMBA is an optional signal in SMBus mode. This signal is not applicable if SMBus is disabled.
2
27.3.2 I C slave mode
By default the I
Master mode a Start condition generation is needed.
The peripheral input clock must be programmed in the I2C_CR2 register in order to
generate correct timings. The peripheral input clock frequency must be at least:
•
2 MHz in Sm mode
•
4 MHz in Fm mode
As soon as a start condition is detected, the address is received from the SDA line and sent
to the shift register. Then it is compared with the address of the interface (OAR1) and with
OAR2 (if ENDUAL=1) or the General Call address (if ENGC = 1).
2
C interface is shown in
Figure 286. I
2
C interface operates in Slave mode. To switch from default Slave mode to
RM0430 Rev 8
Inter-integrated circuit (I
Figure 286.
2
C block diagram
2
C) interface
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