ST STM32F423 Reference Manual page 248

Direct memory access controller (DMA)
Offset Register name
DMA_S6NDTR
0x00A4
Reset value
DMA_S6PAR
0x00A8
Reset value 0
DMA_S6M0AR
0x00AC
Reset value 0
DMA_S6M1AR
0x00B0
Reset value 0
DMA_S6FCR
0x00B4
Reset value
DMA_S7CR
0x00B8
Reset value
DMA_S7NDTR
0x00BC
Reset value
DMA_S7PAR
0x00C0
Reset value 0
DMA_S7M0AR
0x00C4
Reset value 0
DMA_S7M1AR
0x00C8
Reset value 0
DMA_S7FCR
0x00CC
Reset value
Refer to
248/1324
Table 39. DMA register map and reset values (continued)
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
Section 2.2.2 on page 58
0 0
PA[31:0]
0 0 0 0 0 0 0 0 0
M0A[31:0]
0 0 0 0 0 0 0 0 0
M1A[31:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0
PA[31:0]
0 0 0 0 0 0 0 0 0
M0A[31:0]
0 0 0 0 0 0 0 0 0
M1A[31:0]
0 0 0 0 0 0 0 0 0
for the register boundary addresses.
RM0430 Rev 8
NDT[15:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 1
0 0 0 0 0 0 0 0 0
NDT[15:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 1
RM0430
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
FS[2:0]
0 0 0 0 1
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
FS[2:0]
0 0 0 0 1