Dac Output Voltage; Dac Trigger Selection; Table 84. External Triggers; Figure 70. Timing Diagram For Conversion With Trigger Disabled Ten = 0 - ST STM32F423 Reference Manual

Digital-to-analog converter (DAC)
When DAC_DORx is loaded with the DAC_DHRx contents, the analog output voltage
becomes available after a time t
analog output load.

Figure 70. Timing diagram for conversion with trigger disabled TEN = 0

14.3.5

DAC output voltage

Digital inputs are converted to output voltages on a linear conversion between 0 and V
The analog output voltages on each DAC channel pin are determined by the following
equation:
DACoutput
14.3.6

DAC trigger selection

If the TENx control bit is set, conversion can then be triggered by an external event (timer
counter, external interrupt line). The TSELx[2:0] control bits determine which out of 8
possible events will trigger conversion as shown in
Timer 6 TRGO event
Timer 8 TRGO event
Timer 7 TRGO event
Timer 5 TRGO event
Timer 2 TRGO event
Timer 4 TRGO event
EXTI line9
SWTRIG
Each time a DAC interface detects a rising edge on the selected timer TRGO output, or on
the selected external interrupt line 9, the last data stored into the DAC_DHRx register are
transferred into the DAC_DORx register. The DAC_DORx register is updated three APB1
cycles after the trigger occurs.
370/1324
SETTLING
DOR
------------- -
×
V
=
REF
4096

Table 84. External triggers

Source
Internal signal from on-chip
timers
External pin
Software control bit
RM0430 Rev 8
that depends on the power supply voltage and the
Table 84.
Type
RM0430
.
REF+
TSEL[2:0]
000
001
010
011
100
101
110
111