RM0430
Bit number
31:30
29:28
27:24
23:20
19:16
15:8
7:4
3:0
Note:
The FSMC_BWTRx register is valid only if the Extended mode is set (mode B), otherwise its
content is don't care.
Mode C - NOR Flash - OE toggling
Table 57. FSMC_BWTRx bit fields
Bit name
Reserved
0x0
ACCMOD
0x1 if Extended mode is set
DATLAT
Don't care
CLKDIV
Don't care
BUSTURN
Time between NEx high to NEx low (BUSTURN HCLK).
Duration of the access second phase (DATAST HCLK cycles) for
DATAST
write accesses.
ADDHLD
Don't care
Duration of the access first phase (ADDSET HCLK cycles) for write
ADDSET
accesses. Minimum value for ADDSET is 0.
Figure 40. ModeC read access waveforms
RM0430 Rev 8
Flexible static memory controller (FSMC)
Value to set
281/1324
306
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