Adc Sample Time Register 1 (Adc_Smpr1) - ST STM32F423 Reference Manual

Analog-to-digital converter (ADC)
Bit 8 DMA: Direct memory access mode (for single ADC mode)
This bit is set and cleared by software. Refer to the DMA controller chapter for more details.
0: DMA mode disabled
1: DMA mode enabled
Bits 7:2 Reserved, must be kept at reset value.
Bit 1 CONT: Continuous conversion
This bit is set and cleared by software. If it is set, conversion takes place continuously until it
is cleared.
0: Single conversion mode
1: Continuous conversion mode
Bit 0 ADON: A/D Converter ON / OFF
This bit is set and cleared by software.
0: Disable ADC conversion and go to power down mode
1: Enable ADC
13.12.4

ADC sample time register 1 (ADC_SMPR1)

Address offset: 0x0C
Reset value: 0x0000 0000
31 30 29
Res. Res. Res.
15 14 13
SMP15_0 SMP14[2:0]
rw rw rw
Bits 31: 27 Reserved, must be kept at reset value.
Bits 26:0 SMPx[2:0]: Channel x sampling time selection
These bits are written by software to select the sampling time individually for each channel.
During sampling cycles, the channel selection bits must remain unchanged.
Note: 000: 3 cycles
356/1324
28 27 26 25
Res. Res. SMP18[2:0]
rw rw
12 11 10 9
SMP13[2:0]
rw rw rw rw
001: 15 cycles
010: 28 cycles
011: 56 cycles
100: 84 cycles
101: 112 cycles
110: 144 cycles
111: 480 cycles
24 23 22
SMP17[2:0]
rw rw rw
8 7 6
SMP12[2:0]
rw rw rw
RM0430 Rev 8
21 20 19 18
SMP16[2:0]
rw rw rw rw
5 4 3 2
SMP11[2:0]
rw rw rw rw
RM0430
17 16
SMP15[2:1]
rw rw
1 0
SMP10[2:0]
rw rw