Channel-Wise Programmable Sampling Time; Figure 63. Right Alignment Of 12-Bit Data; Figure 64. Left Alignment Of 12-Bit Data; Figure 65. Left Alignment Of 6-Bit Data - ST STM32F423 Reference Manual

Analog-to-digital converter (ADC)
Special case: when left-aligned, the data are aligned on a half-word basis except when the
resolution is set to 6-bit. in that case, the data are aligned on a byte basis as shown in
Figure 65.
13.5

Channel-wise programmable sampling time

The ADC samples the input voltage for a number of ADCCLK cycles that can be modified
using the SMP[2:0] bits in the ADC_SMPR1 and ADC_SMPR2 registers. Each channel can
be sampled with a different sampling time.
The total conversion time is calculated as follows:
T
conv
Example:
With ADCCLK = 30 MHz and sampling time = 3 cycles:
T
conv
344/1324

Figure 63. Right alignment of 12-bit data

Figure 64. Left alignment of 12-bit data

Figure 65. Left alignment of 6-bit data

= Sampling time + 12 cycles
= 3 + 12 = 15 cycles = 0.5 µs with APB2 at 60 MHz
RM0430 Rev 8
RM0430