Fmpi2C Initialization; Figure 256. I2C Bus Protocol - ST STM32F423 Reference Manual

Fast-mode Plus Inter-integrated circuit (FMPI2C) interface
Acknowledge can be enabled or disabled by software. The FMPI2C interface addresses can
be selected by software.
26.4.4

FMPI2C initialization

Enabling and disabling the peripheral
The FMPI2C peripheral clock must be configured and enabled in the clock controller (refer
to Section 6: Reset and clock control (RCC) for
Then the FMPI2C can be enabled by setting the PE bit in the FMPI2C_CR1 register.
When the FMPI2C is disabled (PE=0), the I
Section 26.4.5: Software reset
Noise filters
Before enabling the FMPI2C peripheral by setting the PE bit in FMPI2C_CR1 register, the
user must configure the noise filters, if needed. By default, an analog noise filter is present
on the SDA and SCL inputs. This analog filter is compliant with the I
requires the suppression of spikes with a pulse width up to 50 ns in Fast-mode and Fast-
mode Plus. The user can disable this analog filter by setting the ANFOFF bit, and/or select a
digital filter by configuring the DNF[3:0] bit in the FMPI2C_CR1 register.
When the digital filter is enabled, the level of the SCL or the SDA line is internally changed
only if it remains stable for more than DNF x FMPI2CCLK periods. This allows to suppress
spikes with a programmable length of 1 to 15 FMPI2CCLK periods.
Caution: Changing the filter configuration is not allowed when the FMPI2C is enabled.
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Figure 256. I C bus protocol
STM32F413/423).
2
C performs a software reset. Refer to
for more details.
RM0430 Rev 8
RM0430
2
C specification which