ST STM32F423 Reference Manual page 876

Inter-integrated circuit (I
Bit 9 ARLO: Arbitration lost (master mode)
– Cleared by software writing 0, or by hardware when PE=0.
Note: In SMBUS, the arbitration on the data in slave mode occurs only during the data phase,
Bit 8 BERR: Bus error
– Set by hardware when the interface detects an SDA rising or falling edge while SCL is high,
– Cleared by software writing 0, or by hardware when PE=0.
Bit 7 TxE: Data register empty (transmitters)
– Set when DR is empty in transmission. TxE is not set during address phase.
– Cleared by software writing to the DR register or by hardware after a start or a stop condition
Note: TxE is not cleared by writing the first data being transmitted, or by writing data when
Bit 6 RxNE: Data register not empty (receivers)
– Set when data register is not empty in receiver mode. RxNE is not set during address phase.
– Cleared by software reading or writing the DR register or by hardware when PE=0.
Note: RxNE is not cleared by reading data when BTF is set, as the data register is still full.
Bit 5 Reserved, must be kept at reset value
Bit 4 STOPF: Stop detection (slave mode)
– Set by hardware when a Stop condition is detected on the bus by the slave after an
– Cleared by software reading the SR1 register followed by a write in the CR1 register, or by
Note: The STOPF bit is not set after a NACK reception.
876/1324
2
C) interface
0: No Arbitration Lost detected
1: Arbitration Lost detected
Set by hardware when the interface loses the arbitration of the bus to another master
After an ARLO event the interface switches back automatically to Slave mode (MSL=0).
or the acknowledge transmission (not on the address acknowledge).
0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
occurring in a non-valid position during a byte transfer.
0: Data register not empty
1: Data register empty
or when PE=0.
TxE is not set if either a NACK is received, or if next byte to be transmitted is PEC (PEC=1)
BTF is set, as in both cases the data register is still empty.
0: Data register empty
1: Data register not empty
RxNE is not set in case of ARLO event.
0: No Stop condition detected
1: Stop condition detected
acknowledge (if ACK=1).
hardware when PE=0
It is recommended to perform the complete clearing sequence (READ SR1 then
WRITE CR1) after the STOPF is set. Refer to
for slave receiver on page 854.
RM0430 Rev 8
Figure 288: Transfer sequence diagram
RM0430