Table 128. Initialization Of Aes_Ivrx Registers In Ccm Mode; Figure 249. Ccm Mode Authenticated Decryption - ST STM32F423 Reference Manual

RM0430 AES hardware accelerator (AES)
CCM processing
Figure 249 describes the CCM implementation within the AES peripheral (decryption
example).

Figure 249. CCM mode authenticated decryption

The data input to the generation-encryption process are a valid nonce, a valid payload
string, and a valid associated data string, all properly formatted. The CBC chaining
mechanism is applied to the formatted plaintext data to generate a MAC, with a known
length. Counter mode encryption that requires a sufficiently long sequence of counter blocks
as input, is applied to the payload string and separately to the MAC. The resulting ciphertext
C is the output of the generation-encryption process on plaintext P.
AES_IVRx registers are used for processing each data block, AES automatically
incrementing the CTR counter with a bit length defined by the first block B0. Table 128
shows how the application must load the B0 data.

Table 128. Initialization of AES_IVRx registers in CCM mode

Register AES_IVR3[31:0] AES_IVR2[31:0] AES_IVR1[31:0] AES_IVR0[31:0]
Input data B0[31:0] B0[63:32] B0[95:64] B0[127:96]
RM0430 Rev 8 721/1324
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