Dfsdm Register Map; Table 97. Dfsdm Register Map And Reset Values - ST STM32F423 Reference Manual

Advanced arm-based 32-bit mcus

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Digital filter for sigma delta modulators (DFSDM)

Bits 31:4 CNVCNT[27:0]: 28-bit timer counting conversion time t = CNVCNT[27:0] / f

The timer has an input clock from DFSDM clock (system clock

measurement is started on each conversion start and stopped when conversion finishes (interval

between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion

time measurement stopped and CNVCNT[27:0] = 0. The counted time is:

if FAST=0 (or first conversion in continuous mode if FAST=1):

if FAST=1 in continuous mode (except first conversion):

in case if F

CNVCNT = 0 (counting is stopped, conversion time: t = I

case of parallel data input (from CPU/DMA write)

Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also

this interruption time.

Bits 3:0 Reserved, must be kept at reset value.

DFSDM register map

The following table summarizes the DFSDM registers.

-1 + 4) + 2] / f

= FOSR[9:0]+1 = 1 (filter bypassed, active only integrator):

is the channel input clock frequency (on given channel CKINy pin) or input data rate in

INDAT1[15:0]

..... for Sinc

..... for FastSinc filter

CKOUTDIV[7:0]

OFFSET[23:0]

RM0430 Rev 8

). Conversion time

INDAT0[15:0]

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