ST STM32F423 Reference Manual page 178

Reset and clock control (RCC) for STM32F413/423
Bits 23:22 SAII1BSRC: SAI1 B clock selection
Bits 21:20 SAII1ASRC: SAI1 A clock selection
Bits 19: 16 Reserved, must be kept at reset value.
Bit 15 CKDFSDM1ASEL: DFSDM1 audio clock selection.
Bit 14 CKDFSDM2ASEL: DFSDM2 audio clock selection.
Bit 13 Reserved, must be kept at reset value.
Bits 12:8 PLLDIVR: PLL division factor for SAI1 A/B clock
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 PLLI2SDIVR: PLLI2S division factor for SAI1 A/B clock
178/1324
Set and reset by software.
00: PLLI2S_R divided (R2) as SAI1 B clock
01: I2S_CLIN as SAI1 B clock
00: PLL_R divided (R1) as SAI1 B clock
11: HS_CK as SAI1 B clock
Set and reset by software.
00: PLLI2S_R divided (R2) as SAI1 A clock
01: I2S_CLIN as SAI1 A clock
00: PLL_R divided (R1) as SAI1 A clock
11: HS_CK as SAI1 A clock
0: CK_I2S_APB1 selected as audio clock
1: CK_I2S_APB2 selected as audio clock
0: CK_I2S_APB1 selected as audio clock
1: CK_I2S_APB2 selected as audio clock
Set and reset by software to control the division factor of PLL_R1 clock.
These bits should be written when the PLL is disabled.
00000: PLL_R1 = wrong configuration
00001: PLL_R1 = div/1
....
10000: PLL_R1 = div/16
....
11111: PLL_R1 = div/31
Set and reset by software to control the division factor of PLLI2S_R2 clock.
These bits should be written when the PLLI2S is disabled.
00000: PLLI2S_R2 = wrong configuration
00001: PLLI2S_R2 = div/1
....
10000: PLLI2S_R2 = div/16
....
11111: PLLI2S_R2 = div/31
RM0430 Rev 8
RM0430