I2S Full-Duplex; Figure 331. I2S Full-Duplex Block Diagram - ST STM32F423 Reference Manual

Serial peripheral interface/ inter-IC sound (SPI/I2S)
The SPI can function as an audio I
the I2SMOD bit in the SPIx_I2SCFGR register). This interface mainly uses the same pins,
flags and interrupts as the SPI.
2
The I S shares three common pins with the SPI:
•
SD: Serial Data (mapped on the MOSI pin) to transmit or receive the two time-
multiplexed data channels (in half-duplex mode only).
• WS: Word Select (mapped on the NSS pin) is the data control signal output in master
mode and input in slave mode.
•
CK: Serial Clock (mapped on the SCK pin) is the serial clock output in master mode
and serial clock input in slave mode.
An additional pin can be used when a master clock output is needed for some external
audio devices:
•
MCK: Master Clock (mapped separately) is used, when the I
mode (and when the MCKOE bit in the SPIx_I2SPR register is set), to output this
additional clock generated at a preconfigured frequency rate equal to 256 × f
f is the audio sampling frequency.
S
2
The I S uses its own clock generator to produce the communication clock when it is set in
master mode. This clock generator is also the source of the master clock output. Two
additional registers are available in I
configuration SPIx_I2SPR and the other one is a generic I
SPIx_I2SCFGR (audio standard, slave/master mode, data format, packet frame, clock
polarity, etc.).
The SPIx_CR1 register and all CRC registers are not used in the I
SSOE bit in the SPIx_CR2 register and the MODF and CRCERR bits in the SPIx_SR are
not used.
2
The I S uses the same SPI register for data transfer (SPIx_DR) in 16-bit wide mode.
29.6.2

I2S full-duplex

To support I2S full-duplex mode, two extra I
I2S3_ext) are available in addition to I2S2 and I2S3 (see
duplex interface is consequently based on I2S2 and I2S2_ext, and the second one on I2S3
and I2S3_ext.
Note: I2S2_ext an I2S3_ext are used only in full-duplex mode.
1. Where x can be 2 or 3.
960/1324
2
S interface when the I
2
S mode. One is linked to the clock generator
2
S instances called extended I2Ss (I2S2_ext,

Figure 331. I2S full-duplex block diagram

RM0430 Rev 8
2
S capability is enabled (by setting
2
S is configured in master
2
S configuration register
2
S mode. Likewise, the
Figure 331). The first I2S full-
RM0430
, where
S