Table 63. Fsmc_Bwtrx Bit Fields; Figure 44. Muxed Read Access Waveforms - ST STM32F423 Reference Manual

Flexible static memory controller (FSMC)
Bit number
31:30
29:28
27:24
23:20
19:16
15:8
7:4
3:0
Muxed mode - multiplexed asynchronous access to NOR Flash memory
286/1324

Table 63. FSMC_BWTRx bit fields

Bit name
Reserved 0x0
ACCMOD 0x3
DATLAT Don't care
CLKDIV Don't care
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
Duration of the second access phase (DATAST + 1 HCLK cycles) for
DATAST
write accesses.
Duration of the middle phase of the write access (ADDHLD HCLK
ADDHLD
cycles)
Duration of the first access phase (ADDSET HCLK cycles) for write
ADDSET
accesses. Minimum value for ADDSET is 1.

Figure 44. Muxed read access waveforms

RM0430 Rev 8
Value to set
RM0430