ST STM32F423 Reference Manual page 902

Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit-
Table 163. Error calculation for programmed baud rates at f
Baud rate
S.No Desired
8 896 KBps
9 921.6 KBps
1. The lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can
be fixed with these data.
Table 164. Error calculation for programmed baud rates at f
Baud rate
S.No Desired
1 2.4 KBps
2 9.6 KBps
3 19.2 KBps
4 57.6 KBps
5 115.2 KBps
6 230.4 KBps
7 460.8 KBps
8 896 KBps
9 921.6 KBps
10 1.792 MBps
11 1.8432 MBps
1. The lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can
be fixed with these data.
902/1324
oversampling by 16
Oversampling by 16 (OVER8=0)
f = 8 MHz
PCLK
Value
programmed
Actual
in the baud
rate register
NA NA
NA NA
oversampling by 8
Oversampling by 8 (OVER8=1)
f = 8 MHz
PCLK
Value
programmed
Actual
in the baud
rate register
2.400 KBps 416.625
9.604 KBps 104.125
19.185 KBps 52.125
57.557 KBps 17.375
115.942 KBps 8.625
228.571 KBps 4.375
470.588 KBps 2.125
888.889 KBps 1.125
888.889 KBps 1.125
NA NA
NA NA
(1)
(continued)
% Error =
(Calculated -
Desired)B.Rate
/Desired B.Rate
NA
NA
(1)
% Error =
(Calculated -
Desired)B.Rate
/Desired B.Rate
0.01%
0.04%
0.08%
0.08%
0.64%
0.79%
2.12%
0.79%
3.55%
NA
NA
RM0430 Rev 8
= 8 MHz or f
PCLK PCLK
f = 16 MHz
PCLK
Value
programmed
Actual
in the baud
rate register
888.889 KBps 1.1250
941.176 KBps 1.0625
= 8 MHz or f
PCLK PCLK
f = 16 MHz
PCLK
Value
programmed
Actual
in the baud
rate register
2.400 KBps 833.375
9.598 KBps 208.375
19.208 KBps 104.125
57.554 KBps 34.750
115.108 KBps 17.375
231.884 KBps 8.625
457.143 KBps 4.375
888.889 KBps 2.250
941.176 KBps 2.125
1.7777 MBps 1.125
1.7777 MBps 1.125
= 16 MHz,
% Error
0.79%
2.12%
= 16 MHz,
%
Error
0.00%
0.02%
0.04%
0.08%
0.08%
0.64%
0.79%
0.79%
2.12%
0.79%
3.55%