ST STM32F423 Reference Manual page 594

General-purpose timers (TIM2 to TIM5)
Table 108. TIM2 to TIM5 register map and reset values (continued)
Offset Register
TIMx_PSC
0x28
Reset value
TIMx_ARR
0x2C
Reset value
0x30 Reserved
TIMx_CCR1
0x34
Reset value
TIMx_CCR2
0x38
Reset value
TIMx_CCR3
0x3C
Reset value
TIMx_CCR4
0x40
Reset value
0x44 Reserved
TIMx_DCR
0x48
Reset value
TIMx_DMAR
0x4C
Reset value
TIM2_OR
0x50
Reset value
TIM5_OR
0x50
Reset value
Refer to
boundary addresses.
594/1324
ARR[31:16]
(TIM2 and TIM5 only, reserved on the other timers)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCR1[31:16]
(TIM2 and TIM5 only, reserved on the other timers)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCR2[31:16]
(TIM2 and TIM5 only, reserved on the other timers)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCR3[31:16]
(TIM2 and TIM5 only, reserved on the other timers)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCR4[31:16]
(TIM2 and TIM5 only, reserved on the other timers)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Section 2.2.2: Memory map and register boundary addresses
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
RM0430 Rev 8
PSC[15:0]
0 0 0 0 0 0 0 0
ARR[15:0]
0 0 0 0 0 0 0 0
CCR1[15:0]
0 0 0 0 0 0 0 0
CCR2[15:0]
0 0 0 0 0 0 0 0
CCR3[15:0]
0 0 0 0 0 0 0 0
CCR4[15:0]
0 0 0 0 0 0 0 0
DBL[4:0]
0 0 0 0 0
DMAB[15:0]
0 0 0 0 0 0 0 0
ITR1_
RMP
0 0
IT4_
RMP
0 0
for the register
RM0430
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
DBA[4:0]
0 0 0 0 0
0 0 0 0 0