Dma Stream X Peripheral Address Register (Dma_Sxpar); Dma Stream X Memory 0 Address Register (Dma_Sxm0Ar); Dma Stream X Memory 1 Address Register (Dma_Sxm1Ar) - ST STM32F423 Reference Manual

Direct memory access controller (DMA)
9.5.7

DMA stream x peripheral address register (DMA_SxPAR)

Address offset: 0x18 + 0x18 * x, (x = 0 to 7)
Reset value: 0x0000 0000
31 30 29
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15 14 13
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Bits 31:0 PAR[31:0]: peripheral address
9.5.8

DMA stream x memory 0 address register (DMA_SxM0AR)

Address offset: 0x1C + 0x18 * x, (x = 0 to 7)
Reset value: 0x0000 0000
31 30 29
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15 14 13
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Bits 31:0 M0A[31:0]: memory 0 address
9.5.9

DMA stream x memory 1 address register (DMA_SxM1AR)

Address offset: 0x20 + 0x18 * x, (x = 0 to 7)
Reset value: 0x0000 0000
31 30 29
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15 14 13
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242/1324
28 27 26 25
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12 11 10 9
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Base address of the peripheral data register from/to which the data is read/written.
These bits are write-protected and can be written only when bit EN = '0' in the DMA_SxCR
register.
28 27 26 25
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12 11 10 9
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Base address of memory area 0 from/to which the data is read/written.
These bits are write-protected. They can be written only if:
– the stream is disabled (bit EN= '0' in the DMA_SxCR register) or
– the stream is enabled (EN='1' in DMA_SxCR register) and bit CT = '1' in the
DMA_SxCR register (in double-buffer mode).
28 27 26 25
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12 11 10 9
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24 23 22
PAR[31:16]
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8 7 6
PAR[15:0]
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24 23 22
M0A[31:16]
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8 7 6
M0A[15:0]
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24 23 22
M1A[31:16]
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8 7 6
M1A[15:0]
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RM0430 Rev 8
21 20 19 18
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5 4 3 2
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21 20 19 18
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5 4 3 2
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21 20 19 18
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5 4 3 2
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RM0430
17 16
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1 0
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17 16
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1 0
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17 16
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1 0
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