AES hardware accelerator (AES)
1.
Disable the AES peripheral by clearing the EN bit of the AES_CR register
2.
Change the mode to CTR by writing 010 to the CHMOD[2:0] bitfield of the AES_CR
register.
3.
Pad the last block (smaller than 128 bits) with zeros to have a complete block of 128
bits, then write it into AES_DINR register.
4.
Upon encryption completion, read the 128-bit ciphertext from the AES_DOUTR register
and store it as intermediate data.
5.
Change again the mode to GCM by writing 011 to the CHMOD[2:0] bitfield of the
AES_CR register.
6.
Select Final phase by writing 11 to the GCMPH[1:0] bitfield of the AES_CR register.
7.
In the intermediate data, set to zero the bits corresponding to the padded bits of the last
block of payload, then insert the resulting data into AES_DINR register.
8.
Wait for operation completion, and read data on AES_DOUTR. This data is to be
discarded.
9.
Apply the normal Final phase as described in
mode (GCM) on page 712
24.4.7
AES task suspend and resume
A message can be suspended if another message with a higher priority must be processed.
When this highest priority message is sent, the suspended message can resume in both
encryption or decryption mode.
Suspend/resume operations do not break the chaining operation and the message
processing can resume as soon as AES is enabled again to receive the next data block.
Figure 234
order to send a shorter and higher-priority Message 2.
A detailed description of suspend/resume operations is in the sections dedicated to each
AES mode.
704/1324
gives an example of suspend/resume operation: Message 1 is suspended in
Figure 234. Example of suspend mode management
RM0430 Rev 8
Section 24.4.10: AES Galois/counter
RM0430
Need help?
Do you have a question about the STM32F423 and is the answer not in the manual?