Lptim Registers; Lptim Interrupt And Status Register (Lptim_Isr); Table 119. Interrupt Events - ST STM32F423 Reference Manual

Low-power timer (LPTIM)
Interrupt event
Compare match
Auto-reload match
External trigger event
Auto-reload register
update OK
Compare register
update OK
Direction change
21.6

LPTIM registers

21.6.1

LPTIM interrupt and status register (LPTIM_ISR)

Address offset: 0x000
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:22 Reserved, must be kept at reset value.
Bit 21 Reserved, must be kept at reset value.
Bit 20 Reserved, must be kept at reset value.
Bit 19 Reserved, must be kept at reset value.
Bits 18:16 Reserved, must be kept at reset value.
Bit 15 Reserved, must be kept at reset value.
Bit 14 Reserved, must be kept at reset value.
Bit 13 Reserved, must be kept at reset value.
Bit 12 Reserved, must be kept at reset value.
Bit 11 Reserved, must be kept at reset value.
666/1324
Interrupt flag is raised when the content of the Counter register
(LPTIM_CNT) matches the content of the compare register (LPTIM_CMP).
Interrupt flag is raised when the content of the Counter register
(LPTIM_CNT) matches the content of the Auto-reload register
(LPTIM_ARR).
Interrupt flag is raised when an external trigger event is detected
Interrupt flag is raised when the write operation to the LPTIM_ARR register
is complete.
Interrupt flag is raised when the write operation to the LPTIM_CMP register
is complete.
Used in Encoder mode. Two interrupt flags are embedded to signal
direction change:
– UP flag signals up-counting direction change
– DOWN flag signals down-counting direction change.
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.

Table 119. Interrupt events

Description
24 23 22
Res. Res. Res.
8 7 6
Res. Res. DOWN
r
RM0430 Rev 8
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
ARRO CMP EXTTR
UP
K OK IG
r r r r
RM0430
17 16
Res. Res.
1 0
ARRM CMPM
r r