Dfsdm Filter X Module Registers (X=0; Dfsdm Filter X Control Register 1 (Dfsdm_Fltxcr1) - ST STM32F423 Reference Manual

Digital filter for sigma delta modulators (DFSDM)
15.8

DFSDM filter x module registers (x=0..3)

15.8.1

DFSDM filter x control register 1 (DFSDM_FLTxCR1)

Address offset: 0x100 + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000
31 30 29
AWF
Res. FAST Res.
SEL
rw rw
15 14 13
Res. JEXTEN[1:0] Res.
rw rw
Bit 31 Reserved, must be kept at reset value.
Bit 30 AWFSEL: Analog watchdog fast mode select
0: Analog watchdog on data output value (after the digital filter). The comparison is done after offset
correction and shift
1: Analog watchdog on channel transceivers value (after watchdog filter)
Bit 29 FAST: Fast conversion mode selection for regular conversions
0: Fast conversion mode disabled
1: Fast conversion mode enabled
When converting a regular conversion in continuous mode, having enabled the fast mode causes
each conversion (except the first) to execute faster than in standard mode. This bit has no effect on
conversions which are not continuous.
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
if FAST=0 (or first conversion in continuous mode if FAST=1):
t = [F
t = [F
if FAST=1 in continuous mode (except first conversion):
t = [F
in case if F
t = I
OSR
where: f
case of parallel data input.
Bits 28:27 Reserved, must be kept at reset value.
Bits 26:24 RCH[2:0]: Regular channel selection
0: Channel 0 is selected as the regular channel
1: Channel 1 is selected as the regular channel
...
7: Channel 7 is selected as the regular channel
Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is
especially useful in continuous mode (when RCONT=1). It also affects regular conversions which
are pending (due to ongoing injected conversion).
Bits 23:22 Reserved, must be kept at reset value.
426/1324
28 27 26 25
Res. RCH[2:0]
rw rw
12 11 10 9
Res. JEXTSEL[2:0]
rw rw
* (I -1 + F ) + F
OSR OSR ORD
* (I -1 + 4) + 2] / f
OSR OSR
* I ] / f
OSR OSR CKIN
= F [9:0]+1 = 1 (filter bypassed, active only integrator):
OSR OSR
/ f (... but CNVCNT=0)
CKIN
is the channel input clock frequency (on given channel CKINy pin) or input data rate in
CKIN
24 23 22
Res. Res.
rw
8 7 6
Res. Res.
rw
] / f ..... for Sinc
ORD CKIN
..... for FastSinc filter
CKIN
RM0430 Rev 8
21 20 19
RDMA RCON
Res. RSYNC
EN
rw rw
5 4 3
JDMA
JSCAN JSYNC Res.
EN
rw rw rw
x
filters
RM0430
18 17 16
RSW
Res.
T START
rw rt_w1
2 1 0
JSW
DFEN
START
rt_w1 rw