Table 96. Dfsdm Interrupt Requests - ST STM32F423 Reference Manual

RM0430
–
–
–
•
Data overrun interrupt for regular conversions:
–
–
–
–
•
Analog watchdog interrupt:
–
–
–
–
–
•
Short-circuit detector interrupt:
–
–
–
–
• Channel clock absence interrupt:
–
–
–
–
Interrupt event
End of injected conversion
End of regular conversion
Injected data overrun
enabled by JOVRIE bit in DFSDM_FLTxCR2 register
indicated in JOVRF bit in DFSDM_FLTxISR register
cleared by writing '1' into CLRJOVRF bit in DFSDM_FLTxICR register
occurred when regular converted data were not read from DFSDM_FLTxRDATAR
register (by CPU or DMA) and were overwritten by a new regular conversion
enabled by ROVRIE bit in DFSDM_FLTxCR2 register
indicated in ROVRF bit in DFSDM_FLTxISR register
cleared by writing '1' into CLRROVRF bit in DFSDM_FLTxICR register
occurred when converted data (output data or data from analog watchdog filter -
according to AWFSEL bit setting in DFSDM_FLTxCR1 register) crosses
over/under high/low thresholds in DFSDM_FLTxAWHTR / DFSDM_FLTxAWLTR
registers
enabled by AWDIE bit in DFSDM_FLTxCR2 register (on selected channels
AWDCH[7:0])
indicated in AWDF bit in DFSDM_FLTxISR register
separate indication of high or low analog watchdog threshold error by AWHTF[7:0]
and AWLTF[7:0] fields in DFSDM_FLTxAWSR register
cleared by writing '1' into corresponding CLRAWHTF[7:0] or CLRAWLTF[7:0] bits
in DFSDM_FLTxAWCFR register
occurred when the number of stable data crosses over thresholds in
DFSDM_CHyAWSCDR register
enabled by SCDIE bit in DFSDM_FLTxCR2 register (on channel selected by
SCDEN bi tin DFSDM_CHyCFGR1 register)
indicated in SCDF[7:0] bits in DFSDM_FLTxISR register (which also reports the
channel on which the short-circuit detector event occurred)
cleared by writing '1' into the corresponding CLRSCDF[7:0] bit in
DFSDM_FLTxICR register
occurred when there is clock absence on CKINy pin (see
in Section 15.4.4: Serial channel
enabled by CKABIE bit in DFSDM_FLTxCR2 register (on channels selected by
CKABEN bit in DFSDM_CHyCFGR1 register)
indicated in CKABF[y] bit in DFSDM_FLTxISR register
cleared by writing '1' into CLRCKABF[y] bit in DFSDM_FLTxICR register

Table 96. DFSDM interrupt requests

Event flag
JEOCF
REOCF
JOVRF
Digital filter for sigma delta modulators (DFSDM)
transceivers)
Event/Interrupt clearing
reading DFSDM_FLTxJDATAR
reading DFSDM_FLTxRDATAR REOCIE
writing CLRJOVRF = 1
RM0430 Rev 8
Clock absence detection
Interrupt enable
method
JEOCIE
JOVRIE
control bit
419/1324
449