Aes Processing Latency; Table 132. Aes Interrupt Requests; Table 133. Processing Latency (In Clock Cycle) For Ecb, Cbc And Ctr; Table 134. Processing Latency For Gcm And Ccm (In Clock Cycle) - ST STM32F423 Reference Manual

AES hardware accelerator (AES)
The status of the individual maskable interrupt sources can be read from the AES_SR
register.
Table 132
24.6

AES processing latency

The tables below summarize the latency to process a 128-bit block for each mode of
operation.

Table 133. Processing latency (in clock cycle) for ECB, CBC and CTR

Key size Mode of operation
Mode 1: Encryption
Mode 2: Key derivation
128-bit
Mode 3: Decryption
Mode 4: Key derivation then
decryption
Mode 1: Encryption
Mode 2: Key derivation
256-bit
Mode 3: Decryption
Mode 4: Key derivation then
decryption

Table 134. Processing latency for GCM and CCM (in clock cycle)

Key size Mode of operation
Mode 1: Encryption/
Mode 3: Decryption
128-bit
Mode 1: Encryption/
Mode 3: Decryption
256-bit
730/1324
gives a summary of the interrupt sources, their event flags and enable bits.

Table 132. AES interrupt requests

AES interrupt event
computation completed flag
read error flag
write error flag
Algorithm
GCM
CCM
-
authentication
GCM
CCM
-
authentication
Input
Algorithm
phase
ECB, CBC, CTR 8
- -
ECB, CBC, CTR 8
ECB, CBC 8
ECB, CBC, CTR 8
- -
ECB, CBC, CTR 8
ECB, CBC 8
Init Phase
215
-
299
-
RM0430 Rev 8
Event flag Enable bit
CCF
RDERR
WRERR
Computation Output
phase phase
202
80
202
276
286
109
286
380
Header Payload
phase phase
67 202
206 -
67 286
290 -
RM0430
CCFIE
ERRIE
ERRIE
Total
4 214
- 80
4 214
4 288
4 298
- 109
4 298
4 392
Tag phase
202
202
286
286