ST STM32F423 Reference Manual page 894

Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit-
The RXNE flag is set after every byte received. An overrun error occurs if RXNE flag is set
when the next data is received or the previous DMA request has not been serviced. When
an overrun error occurs:
•
The ORE bit is set.
• The RDR content will not be lost. The previous data is available when a read to
USART_DR is performed.
•
The shift register will be overwritten. After that point, any data received during overrun
is lost.
•
An interrupt is generated if either the RXNEIE bit is set or both the EIE and DMAR bits
are set.
• The ORE bit is reset by a read to the USART_SR register followed by a USART_DR
register read operation.
Note: The ORE bit, when set, indicates that at least 1 data has been lost. There are two
possibilities:
•
if RXNE=1, then the last valid data is stored in the receive register RDR and can be
read,
•
if RXNE=0, then it means that the last valid data has already been read and thus there
is nothing to be read in the RDR. This case can occur when the last valid data is read in
the RDR at the same time as the new (and lost) data is received. It may also occur
when the new data is received during the reading sequence (between the USART_SR
register read access and the USART_DR read access).
Selecting the proper oversampling method
The receiver implements different user-configurable oversampling techniques (except in
synchronous mode) for data recovery by discriminating between valid incoming data and
noise.
The oversampling method can be selected by programming the OVER8 bit in the
USART_CR1 register and can be either 16 or 8 times the baud rate clock
Figure 298).
Depending on the application:
•
select oversampling by 8 (OVER8=1) to achieve higher speed (up to f
case the maximum receiver tolerance to clock deviation is reduced (refer to
Section 28.4.5: USART receiver tolerance to clock
• select oversampling by 16 (OVER8=0) to increase the tolerance of the receiver to clock
deviations. In this case, the maximum speed is limited to maximum f
Programming the ONEBIT bit in the USART_CR3 register selects the method used to
evaluate the logic level. There are two options:
•
the majority vote of the three samples in the center of the received bit. In this case,
when the 3 samples used for the majority vote are not equal, the NF bit is set
•
a single sample in the center of the received bit
Depending on the application:
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select the three samples' majority vote method (ONEBIT=0) when operating in a
noisy environment and reject the data when a noise is detected (refer to
Figure 158) because this indicates that a glitch occurred during the sampling.
select the single sample method (ONEBIT=1) when the line is noise-free to
increase the receiver tolerance to clock deviations (see
RM0430 Rev 8
(Figure 297
PCLK
deviation)
PCLK
Section 28.4.5: USART
and
/8). In this
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