ST STM32F423 Reference Manual page 302

Flexible static memory controller (FSMC)
Bits 7:4 ADDHLD[3:0]: Address-hold phase duration
These bits are written by software to define the duration of the address hold phase (refer to
Figure 33
0000: Reserved
0001: ADDHLD phase duration =1 × HCLK clock cycle
0010: ADDHLD phase duration = 2 × HCLK clock cycle
...
1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
For each access mode address-hold phase duration, refer to the respective figure
to
Note: In synchronous accesses, this value is not used, the address hold phase is always 1
Bits 3:0 ADDSET[3:0]: Address setup phase duration
These bits are written by software to define the duration of the address setup phase (refer to
Figure 33
0000: ADDSET phase duration = 0 × HCLK clock cycle
...
1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)
For each access mode address setup phase duration, refer to the respective figure
(Figure 33
Note: In synchronous accesses, this value is don't care.
Note: PSRAMs (CRAMs) have a variable latency due to internal refresh. Therefore these
memories issue the NWAIT signal during the whole latency phase to prolong the latency as
needed.
With PSRAMs (CRAMs) the filled DATLAT must be set to 0, so that the FSMC exits its
latency phase soon and starts sampling NWAIT from memory, then starts to read or write
when the memory is ready.
This method can be used also with the latest generation of synchronous Flash memories
that issue the NWAIT signal, unlike older Flash memories (check the datasheet of the
specific Flash memory being used).
SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTR1..4)
Address offset: 0x104 + 8 * (x – 1), x = 1...4
Reset value: 0x0FFF FFFF
This register contains the control information of each memory bank. It is used for SRAMs,
PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FSMC_BCRx
register, then this register is active for write access.
31 30 29
Res. Res. ACCMOD[1:0]
rw
15 14 13
rw rw rw
Bits 31:30 Reserved, must be kept at reset value.
302/1324
to Figure 45), used in mode D or multiplexed accesses:
Figure 45).
memory clock period duration.
to Figure 45), used in SRAMs, ROMs, asynchronous NOR Flash and PSRAM:
to Figure 45).
In Muxed mode or Mode D, the minimum value for ADDSET is 1.
In mode 1 and PSRAM memory, the minimum value for ADDSET is 1.
28 27 26 25
Res. Res. Res.
rw
12 11 10 9
DATAST[7:0]
rw rw rw rw
24 23 22
Res. Res. Res.
8 7 6
ADDHLD[3:0]
rw rw rw
RM0430 Rev 8
21 20 19 18
Res. Res. BUSTURN[3:0]
rw rw
5 4 3 2
ADDSET[3:0]
rw rw rw rw
RM0430
(Figure 33
17 16
rw rw
1 0
rw rw