Single-Wire Half-Duplex Communication; Figure 305. Usart Data Clock Timing Diagram (M=1); Figure 306. Rx Data Setup/Hold Time - ST STM32F423 Reference Manual

Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit-
Note: The function of SCLK is different in Smartcard mode. Refer to the Smartcard mode chapter
for more details.
28.4.10

Single-wire half-duplex communication

The single-wire half-duplex mode is selected by setting the HDSEL bit in the USART_CR3
register. In this mode, the following bits must be kept cleared:
•
LINEN and CLKEN bits in the USART_CR2 register,
•
SCEN and IREN bits in the USART_CR3 register.
The USART can be configured to follow a single-wire half-duplex protocol where the TX and
RX lines are internally connected. The selection between half- and full-duplex
communication is made with a control bit 'HALF DUPLEX SEL' (HDSEL in USART_CR3).
914/1324

Figure 305. USART data clock timing diagram (M=1)

Figure 306. RX data setup/hold time

RM0430 Rev 8