ST STM32F423 Reference Manual page 12

Contents
14.3.9
14.4 Dual DAC channel conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
14.4.1
14.4.2
14.4.3
14.4.4
14.4.5
14.4.6
14.4.7
14.4.8
14.4.9
14.4.10 Simultaneous trigger with single triangle generation . . . . . . . . . . . . . . 377
14.4.11 Simultaneous trigger with different triangle generation . . . . . . . . . . . . 377
14.5 DAC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
14.5.1
14.5.2
14.5.3
14.5.4
14.5.5
14.5.6
14.5.7
14.5.8
14.5.9
14.5.10 DUAL DAC 12-bit left aligned data holding register
14.5.11 DUAL DAC 8-bit right aligned data holding register
14.5.12 DAC channel1 data output register (DAC_DOR1) . . . . . . . . . . . . . . . . 385
14.5.13 DAC channel2 data output register (DAC_DOR2) . . . . . . . . . . . . . . . . 385
14.5.14 DAC status register (DAC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
14.5.15 DAC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
15 Digital filter for sigma delta modulators (DFSDM) . . . . . . . . . . . . . . . 388
12/1324
Triangle-wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Independent trigger without wave generation . . . . . . . . . . . . . . . . . . . 374
Independent trigger with single LFSR generation . . . . . . . . . . . . . . . . 374
Independent trigger with different LFSR generation . . . . . . . . . . . . . . 374
Independent trigger with single triangle generation . . . . . . . . . . . . . . . 375
Independent trigger with different triangle generation . . . . . . . . . . . . . 375
Simultaneous software start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
Simultaneous trigger without wave generation . . . . . . . . . . . . . . . . . . 376
Simultaneous trigger with single LFSR generation . . . . . . . . . . . . . . . 376
Simultaneous trigger with different LFSR generation . . . . . . . . . . . . . 376
DAC control register (DAC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
DAC software trigger register (DAC_SWTRIGR) . . . . . . . . . . . . . . . . . 381
DAC channel1 12-bit right-aligned data holding register
(DAC_DHR12R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
DAC channel1 12-bit left aligned data holding register
(DAC_DHR12L1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
DAC channel1 8-bit right aligned data holding register
(DAC_DHR8R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
DAC channel2 12-bit right aligned data holding register
(DAC_DHR12R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
DAC channel2 12-bit left aligned data holding register
(DAC_DHR12L2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
DAC channel2 8-bit right-aligned data holding register
(DAC_DHR8R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
Dual DAC 12-bit right-aligned data holding register
(DAC_DHR12RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
(DAC_DHR12LD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
(DAC_DHR8RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
RM0430 Rev 8
RM0430