Fsmc Register Map; Table 70. Fsmc Register Map - ST STM32F423 Reference Manual

Advanced arm-based 32-bit mcus
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RM0430
11.6

FSMC register map

Offset
Register
FSMC_BCR1
0x00
Reset value
FSMC_BCR2
0x08
Reset value
FSMC_BCR3
0x10
Reset value
FSMC_BCR4
0x18
Reset value
FSMC_BTR1
0x04
Reset value
FSMC_BTR2
0x0C
Reset value
FSMC_BTR3
0x14
Reset value
FSMC_BTR4
0x1C
Reset value
FSMC_BWTR1
0x104
Reset value
FSMC_BWTR2
0x10C
Reset value

Table 70. FSMC register map

0
DATLAT[3:0]
CLKDIV[3:0] BUSTURN[3:0]
0
0
1
1
1
1
1
1
1
DATLAT[3:0]
CLKDIV[3:0] BUSTURN[3:0]
0
0
1
1
1
1
1
1
1
DATLAT[3:0]
CLKDIV[3:0] BUSTURN[3:0]
0
0
1
1
1
1
1
1
1
DATLAT[3:0]
CLKDIV[3:0] BUSTURN[3:0]
0
0
1
1
1
1
1
1
1
0
0
0
0
RM0430 Rev 8
Flexible static memory controller (FSMC)
CPSIZE
[2:0]
0
0
0
0
0
0
0
1
CPSIZE
[2:0]
0
0
0
0
0
0
1
CPSIZE
[2:0]
0
0
0
0
0
0
1
CPSIZE
[2:0]
0
0
0
0
0
0
1
DATAST[7:0]
1
1
1
1
1
1
1
1
DATAST[7:0]
1
1
1
1
1
1
1
1
DATAST[7:0]
1
1
1
1
1
1
1
1
DATAST[7:0]
1
1
1
1
1
1
1
1
BUSTURN[3:0]
DATAST[7:0]
1
1
1
1
1
1
1
BUSTURN[3:0]
DATAST[7:0]
1
1
1
1
1
1
1
MWID
[1:0]
1
0
0
0
1
0
MWID
[1:0]
1
0
0
0
1
0
MWID
[1:0]
1
0
0
0
1
0
MWID
[1:0]
1
0
0
0
1
0
ADDHLD[3:0] ADDSET[3:0]
1
1
1
1
1
1
1
1
ADDHLD[3:0] ADDSET[3:0]
1
1
1
1
1
1
1
1
ADDHLD[3:0] ADDSET[3:0]
1
1
1
1
1
1
1
1
ADDHLD[3:0] ADDSET[3:0]
1
1
1
1
1
1
1
1
ADDHLD[3:0] ADDSET[3:0]
1
1
1
1
1
1
1
1
ADDHLD[3:0] ADDSET[3:0]
1
1
1
1
1
1
1
1
MTYP
[1:0]
1
1
0
1
1
MTYP
[1:0]
1
0
0
1
0
MTYP
[1:0]
1
0
0
1
0
MTYP
[1:0]
1
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
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