ST STM32F423 Reference Manual page 441

RM0430
Table 97. DFSDM register map and reset values (continued)
Register
Offset
name
DFSDM_
CH1CFGR2
0x24
reset value 0
DFSDM_
CH1AWSCDR
0x28
reset value
DFSDM_
CH1WDATR
0x2C
reset value
DFSDM_
CH1DATINR
0x30
reset value 0
0x34 -
Reserved
0x3C
DFSDM_
CH2CFGR1
0x40
reset value
DFSDM_
CH2CFGR2
0x44
reset value 0
DFSDM_
CH2AWSCDR
0x48
reset value
DFSDM_
CH2WDATR
0x4C
reset value
DFSDM_
CH2DATINR
0x50
reset value 0
0x54 -
Reserved
0x5C
DFSDM_
CH3CFGR1
0x60
reset value
DFSDM_
CH3CFGR2
0x64
reset value 0
0 0 0 0 0 0 0 0 0
0 0
INDAT1[15:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0
INDAT1[15:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
Digital filter for sigma delta modulators (DFSDM)
OFFSET[23:0]
0 0 0 0 0 0 0 0
AWFOSR[4:0] BKSCD[3:0]
0 0 0 0 0 0 0
0 0 0
0 0 0 0 0 0 0 0
0 0
OFFSET[23:0]
0 0 0 0 0 0 0 0
AWFOSR[4:0] BKSCD[3:0]
0 0 0 0 0 0 0
0 0
0 0 0 0 0 0 0 0
0 0
OFFSET[23:0]
0 0 0 0 0 0 0 0
RM0430 Rev 8
DTRBS[4:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0
WDATA[15:0]
0 0 0 0 0 0 0 0 0
INDAT0[15:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0
DTRBS[4:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0
WDATA[15:0]
0 0 0 0 0 0 0 0 0
INDAT0[15:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0
DTRBS[4:0]
0 0 0 0 0 0 0 0 0
0 0
SCDT[7:0]
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0
0 0
SCDT[7:0]
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0
0 0
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