Table 127. Gcm Mode Ivi Bitfield Initialization; Figure 245. Gcm Authenticated Encryption - ST STM32F423 Reference Manual

AES hardware accelerator (AES)
GCM processing
Figure 245
by writing 011 to the CHMOD[2:0] bitfield of the AES_CR register.
The mechanism for the confidentiality of the plaintext in GCM mode is similar to that in the
Counter mode, with a particular increment function (denoted 32-bit increment) that
generates the sequence of input counter blocks.
AES_IVRx registers keeping the counter block of data are used for processing each data
block. The AES peripheral automatically increments the Counter[31:0] bitfield. The first
counter block (CB1) is derived from the initial counter block ICB by the application software
(see Table
Register
Input data
Note: In GCM mode, the settings 01 and 11 of the MODE[1:0] bitfield are forbidden.
714/1324
describes the GCM implementation in the AES peripheral. The GCM is selected

Figure 245. GCM authenticated encryption

127).

Table 127. GCM mode IVI bitfield initialization

AES_IVR3[31:0] AES_IVR2[31:0]
ICB[31:0]
AES_IVR1[31:0]
ICB[63:32]
RM0430 Rev 8
AES_IVR0[31:0]
ICB[95:64] Counter[31:0] = 0x2
RM0430