ST STM32F423 Reference Manual page 402

Digital filter for sigma delta modulators (DFSDM)
Note: When conversion is interrupted (e.g. by disabling/enabling the selected channel) the
interruption time is also counted in CNVCNT[27:0]. Therefore it is recommended to not
interrupt the conversion for correct conversion duration result.
Conversion times:
injected conversion or regular conversion with FAST = 0 (or first conversion if
FAST=1):
for Sinc
for FastSinc filter:
regular conversion with FAST = 1 (except first conversion):
for Sinc
in case if F
where:
• f
CKIN
rate (in case of parallel data input)
•
F
OSR
register)
•
I
OSR
register)
•
F
ORD
Channel offset setting
Each channel has its own offset setting (in register) which is finally subtracted from each
conversion result (injected or regular) from a given channel. Offset correction is performed
after the data right bit shift. The offset is stored as a 24-bit signed value in OFFSET[23:0]
field in DFSDM_CHyCFGR2 register.
Data right bit shift
To have the result aligned to a 24-bit value, each channel defines a number of right bit shifts
which will be applied on each conversion result (injected or regular) from a given channel.
The data bit shift number is stored in DTRBS[4:0] bits in DFSDM_CHyCFGR2 register.
The right bit-shift is rounding the result to nearest integer value. The sign of shifted result is
maintained, in order to have valid 24-bit signed format of result data.
Pulses skipper
Purpose of the pulses skipper is to implement delay line like behavior for given input
channel(s). Given number of samples from input serial data stream (serial stream only) can
be discarded before they enter into the filter. This data discarding is performed by skipping
given number of sampling input clock pulses (given serial data samples are then not
sampled by filter). The sampling clock is gated by pulses skipper function for given number
of clock pulses. When given clock pulses are skipped then the filtering continues for
following input data. With comparison to non skipped data stream this operation causes that
402/1324
x
filters (x=1..5):
t = CNVCNT/f
DFSDMCLK
t = CNVCNT/f
DFSDMCLK
x
and FastSinc filters:
t = CNVCNT/f
DFSDMCLK
= FOSR[9:0]+1 = 1 (filter bypassed, active only integrator):
OSR
t = I / f (... but CNVCNT=0)
OSR CKIN
is the channel input clock frequency (on given channel CKINy pin) or input data
is the filter oversampling ratio: F
is the integrator oversampling ratio: I
is the filter order: F
ORD
= [F * (I -1 + F
OSR OSR
= [F * (I -1 + 4) + 2] / f
OSR OSR
= [F * I ] / f
OSR OSR CKIN
= FOSR[9:0]+1 (see DFSDM_FLTxFCR
OSR
= IOSR[7:0]+1 (see DFSDM_FLTxFCR
OSR
= FORD[2:0] (see DFSDM_FLTxFCR register)
RM0430 Rev 8
) + F ] / f
ORD ORD CKIN
CKIN
RM0430