Timing Diagram; Analog Watchdog; Figure 60. Timing Diagram; Figure 61. Analog Watchdog's Guarded Area - ST STM32F423 Reference Manual

Analog-to-digital converter (ADC)
mode (using JAUTO bit), refer to
13.3.6

Timing diagram

As shown in
converting accurately. After the start of the ADC conversion and after 15 clock cycles, the
EOC flag is set and the 16-bit ADC data register contains the result of the conversion.
13.3.7

Analog watchdog

The AWD analog watchdog status bit is set if the analog voltage converted by the ADC is
below a lower threshold or above a higher threshold. These thresholds are programmed in
the 12 least significant bits of the ADC_HTR and ADC_LTR 16-bit registers. An interrupt can
be enabled by using the AWDIE bit in the ADC_CR1 register.
The threshold value is independent of the alignment selected by the ALIGN bit in the
ADC_CR2 register. The analog voltage is compared to the lower and higher thresholds
before alignment.
Table 75
watchdog on one or more channels.
340/1324
Figure 60, the ADC needs a stabilization time of t

Figure 60. Timing diagram

shows how the ADC_CR1 register should be configured to enable the analog

Figure 61. Analog watchdog's guarded area

Auto-injection section)
RM0430 Rev 8
.
before it starts
STAB
RM0430