ST STM32F423 Reference Manual page 240

Direct memory access controller (DMA)
Bits 12:11 PSIZE[1:0]: peripheral data size
Bit 10 MINC: memory increment mode
Bit 9 PINC: peripheral increment mode
Bit 8 CIRC: circular mode
Bits 7:6 DIR[1:0]: data transfer direction
Bit 5 PFCTRL: peripheral flow controller
Bit 4 TCIE: transfer complete interrupt enable
Bit 3 HTIE: half transfer interrupt enable
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These bits are set and cleared by software.
00: byte (8-bit)
01: half-word (16-bit)
10: word (32-bit)
11: reserved
These bits are protected and can be written only if EN is '0'.
This bit is set and cleared by software.
0: memory address pointer is fixed
1: memory address pointer is incremented after each data transfer (increment is done
according to MSIZE)
This bit is protected and can be written only if EN is '0'.
This bit is set and cleared by software.
0: peripheral address pointer is fixed
1: peripheral address pointer is incremented after each data transfer (increment is done
according to PSIZE)
This bit is protected and can be written only if EN is '0'.
This bit is set and cleared by software and can be cleared by hardware.
0: circular mode disabled
1: circular mode enabled
When the peripheral is the flow controller (bit PFCTRL = 1) and the stream is enabled (bit
EN = 1), then this bit is automatically forced by hardware to 0.
It is automatically forced by hardware to 1 if the DBM bit is set, as soon as the stream is
enabled (bit EN ='1').
These bits are set and cleared by software.
00: peripheral-to-memory
01: memory-to-peripheral
10: memory-to-memory
11: reserved
These bits are protected and can be written only if EN is '0'.
This bit is set and cleared by software.
0: DMA is the flow controller
1: The peripheral is the flow controller
This bit is protected and can be written only if EN is '0'.
When the memory-to-memory mode is selected (bits DIR[1:0]=10), then this bit is
automatically forced to 0 by hardware.
This bit is set and cleared by software.
0: TC interrupt disabled
1: TC interrupt enabled
This bit is set and cleared by software.
0: HT interrupt disabled
1: HT interrupt enabled
RM0430 Rev 8
RM0430