ST STM32F423 Reference Manual page 5

RM0430
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
6.3.10
6.3.11
6.3.12
6.3.13
6.3.14
6.3.15
6.3.16
6.3.17
6.3.18
6.3.19
6.3.20
6.3.21
6.3.22
6.3.23
6.3.24
6.3.25
6.3.26
6.3.27
6.3.28
6.3.29
6.3.30
7 General-purpose I/Os (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
RCC clock interrupt register (RCC_CIR) . . . . . . . . . . . . . . . . . . . . . . . 136
RCC AHB1 peripheral reset register (RCC_AHB1RSTR) . . . . . . . . . . 138
RCC AHB2 peripheral reset register (RCC_AHB2RSTR)
for STM32F413xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
RCC AHB2 peripheral reset register (RCC_AHB2RSTR)
for STM32F423xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
RCC AHB3 peripheral reset register (RCC_AHB3RSTR) . . . . . . . . . . 142
RCC APB1 peripheral reset register for (RCC_APB1RSTR) . . . . . . . 142
RCC APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . 146
RCC AHB1 peripheral clock enable register (RCC_AHB1ENR) . . . . . 149
RCC AHB2 peripheral clock enable register (RCC_AHB2ENR)
for STM32F413xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
RCC AHB2 peripheral clock enable register (RCC_AHB2ENR)
for STM32F423xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
RCC AHB3 peripheral clock enable register (RCC_AHB3ENR) . . . . . 153
RCC APB1 peripheral clock enable register (RCC_APB1ENR) . . . . . 153
RCC APB2 peripheral clock enable register
(RCC_APB2ENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
RCC AHB1 peripheral clock enable in low power mode register
(RCC_AHB1LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
RCC AHB2 peripheral clock enable in low power mode register
(RCC_AHB2LPENR) for STM32F413xx . . . . . . . . . . . . . . . . . . . . . . . 162
RCC AHB2 peripheral clock enable in low power mode register
(RCC_AHB2LPENR) for STM32F423xx . . . . . . . . . . . . . . . . . . . . . . . 163
RCC AHB3 peripheral clock enable in low power mode register
(RCC_AHB3LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
RCC APB1 peripheral clock enable in low power mode register
(RCC_APB1LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
RCC APB2 peripheral clock enabled in low power mode register
(RCC_APB2LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
RCC Backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . 171
RCC clock control & status register (RCC_CSR) . . . . . . . . . . . . . . . . 172
RCC spread spectrum clock generation register (RCC_SSCGR) . . . . 174
RCC PLLI2S configuration register (RCC_PLLI2SCFGR) . . . . . . . . . 175
RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR) . . 177
RCC clocks gated enable register (CKGATENR) . . . . . . . . . . . . . . . . 179
RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR2) . 180
RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
RM0430 Rev 8
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