Dma Interrupts; Table 38. Dma Interrupt Requests - ST STM32F423 Reference Manual

Direct memory access controller (DMA)
9.4

DMA interrupts

For each DMA stream, an interrupt can be produced on the following events:
•
Half-transfer reached
• Transfer complete
•
Transfer error
• FIFO error (overrun, underrun or FIFO level error)
•
Direct mode error
Separate interrupt enable control bits are available for flexibility as shown in
Half-transfer
Transfer complete
Transfer error
FIFO overrun/underrun
Direct mode error
Note: Before setting an enable control bit EN = 1, the corresponding event flag must be cleared,
otherwise an interrupt is immediately generated.
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Table 38. DMA interrupt requests

Interrupt event
RM0430 Rev 8
Event flag
HTIF
TCIF
TEIF
FEIF
DMEIF
RM0430
Table 38.
Enable control bit
HTIE
TCIE
TEIE
FEIE
DMEIE