ST STM32F423 Reference Manual page 443

RM0430
Table 97. DFSDM register map and reset values (continued)
Register
Offset
name
DFSDM_
CH5WDATR
0xAC
reset value
DFSDM_
CH5DATINR
0xB0
reset value 0
0xB4 -
Reserved
0xBC
DFSDM_
CH6CFGR1
0xC0
reset value
DFSDM_
CH6CFGR2
0xC4
reset value 0
DFSDM_
CH6AWSCDR
0xC8
reset value
DFSDM_
CH6WDATR
0xCC
reset value
DFSDM_
CH6DATINR
0xD0
reset value 0
0xD4 -
Reserved
0xDC
DFSDM_
CH7CFGR1
0xE0
reset value
DFSDM_
CH7CFGR2
0xE4
reset value 0
DFSDM_
CH7AWSCDR
0xE8
reset value
DFSDM_
CH7WDATR
0xEC
reset value
DFSDM_
CH7DATINR
0xF0
reset value 0
INDAT1[15:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0
INDAT1[15:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0
INDAT1[15:0]
0 0 0 0 0 0 0 0 0
Digital filter for sigma delta modulators (DFSDM)
0 0
0 0 0 0 0 0 0 0
0 0
OFFSET[23:0]
0 0 0 0 0 0 0 0
AWFOSR[4:0] BKSCD[3:0]
0 0 0 0 0 0 0
0 0
0 0 0 0 0 0 0 0
0 0
OFFSET[23:0]
0 0 0 0 0 0 0 0
AWFOSR[4:0] BKSCD[3:0]
0 0 0 0 0 0 0
0 0
0 0 0 0 0 0 0 0
RM0430 Rev 8
WDATA[15:0]
0 0 0 0 0 0 0 0 0
INDAT0[15:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0
DTRBS[4:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0
WDATA[15:0]
0 0 0 0 0 0 0 0 0
INDAT0[15:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0
DTRBS[4:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0
WDATA[15:0]
0 0 0 0 0 0 0 0 0
INDAT0[15:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0
0 0
SCDT[7:0]
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0
0 0
SCDT[7:0]
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
443/1324
449