Figure 287. Transfer Sequence Diagram For Slave Transmitter - ST STM32F423 Reference Manual

RM0430
1. The EV1 and EV3_1 events stretch SCL low until the end of the corresponding software sequence.
2. The EV3 event stretches SCL low if the software sequence is not completed before the end of the next byte
transmission
Slave receiver
Following the address reception and after clearing ADDR, the slave receives bytes from the
SDA line into the DR register via the internal shift register. After each byte the interface
generates in sequence:
•
An acknowledge pulse if the ACK bit is set
•
The RxNE bit is set by hardware and an interrupt is generated if the ITEVFEN and
ITBUFEN bit is set.
If RxNE is set and the data in the DR register is not read before the end of the next data
reception, the BTF bit is set and the interface waits until BTF is cleared by a read from the
I2C_DR register, stretching SCL low (see

Figure 287. Transfer sequence diagram for slave transmitter

RM0430 Rev 8
Inter-integrated circuit (I
Figure 288 Transfer sequencing).
2
C) interface
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