AES hardware accelerator (AES)
A typical message construction for GMAC is given in
AES GMAC processing
Figure 247
selected by writing 011 to the CHMOD[2:0] bitfield of the AES_CR register.
The GMAC algorithm corresponds to the GCM algorithm applied on a message only
containing a header. As a consequence, all steps and settings are the same as with the
GCM, except that the payload phase is omitted.
Suspend/resume operations in GMAC
In GMAC mode, the sequence described for the GCM applies except that only the header
phase can be interrupted.
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Figure 246. Message construction in GMAC mode
describes the GMAC mode implementation in the AES peripheral. This mode is
Figure 247. GMAC authentication mode
RM0430 Rev 8
Figure
246.
RM0430
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