Generation Of Receive Interrupt And Timing Of Flag Set - Fujitsu MB90895 Series Hardware Manual

14.4.1

Generation of Receive Interrupt and Timing of Flag Set

Interrupts during reception are one generated upon completion of reception
(SSR:RDRF) and one generated upon occurrence of a reception error (SSR:PE, ORE,
FRE).
I Generation of Receive Interrupt and Timing of Flag Set
G
Receive data load flag and each receive error flag sets
When data is received, it is stored in serial input data register 0 (SIDR0) upon detection of the stop bit (in
operation mode 0 or 1) or of the data's last bit (SIDR0: D7) (in operation mode 2).When a reception error
occurs, the corresponding error flag (SSR0:PE, ORE, or FRE) is set and the receive data load flag (SSR0:
RDRF) is set as well.In each operation mode, the received data in the serial input data register 0 (SIDR0) is
invalid if either error flag is set.
Operation mode 0 (Asynchronous normal mode)
The receive data load flag bit (SSR0: RDRF) is set upon detection of the stop bit.When a reception occurs,
the error flag (SSR0: ORE) is set.
Operating mode 1 (asynchronous multiprocessor mode)
The receive data load flag bit (SSR0: RDRF) is set when the stop bit is detected.When a reception occurs,
the error flag (SSR0: ORE) is set.But parity errors cannot be detected.
Operating mode 2 (clock synchronous mode)
The receive data load flag bit (SSR0: RDRF) is set to 1 upon detection of the last bit (SIDR0: D7) of the
received data.When a reception occurs, the error flag (SSR0: ORE) is set.Neither a parity error (SSR0: PE)
nor a framing error (SSR0: FRE) can be detected.
CHAPTER 14 UART0
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