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10.3.3
PPG0/1 count clock select register (PPG01)
The PPG0/1 count clock select register (PPG01) selects the count clock of the 8-/16-bit
PPG timer.
I PPG0/1 count clock select register (PPG01)
7
6
5
R/W
R/W
R/W
R/W
: Read/Write
X
: Undefined
-
: Unused
: Reset value
HCLK
: Oscillation clock
φ
: Machine clock frequency
HCLK=4MHz in ( ), value of operating at φ =16MHz
Figure 10.3-4 PPG0/1 count clock select register (PPG01)
4
3
2
1
0
R/W
R/W
R/W
-
-
bit4
PCM2
bit7
PCS2
Reset value
0 0 0 0 0 0 X X
B
bit3
bit2
PCM1
PCM0
PPG0 counter clock select bit
φ (
0
0
0
1/
62.5ns)
φ (
0
0
1
2/
125ns)
φ (
0
1
0
2
2
/
250ns)
φ (
0
1
1
3
2
/
500ns)
φ (
µ
1
0
0
4
2
/
1
s)
1
0
1
Setting disabled
1
1
0
Setting disabled
1
1
1
9
2
/HCLK (128
bit6
bit5
PCS1
PCS0
PPG1 counter clock select bit
φ (
0
0
0
1/
62.5ns)
φ (
0
0
1
2/
125ns)
φ (
0
1
0
2
2
/
250ns)
φ (
0
1
1
3
2
/
500ns)
φ (
µ
1
0
0
4
2
/
1
s)
1
0
1
Setting disabled
1
1
0
Setting disabled
1
1
1
9
2
/HCLK (128
CHAPTER 10 8/16-bit PPG timer
µ
s)
µ
s)
305
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