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19.5
How to Start Automatic Algorithm of Flash Memory
There are four commands for starting the automatic algorithm of flash memory: read/
reset, write, chip erase. The sector erase command controls suspension and
resumption.
I Command Sequence Table
Table 19.5-1 lists the commands to be used to program or erase the flash memory. You can write
to the command register both in bytes and in words. The upper byte written by word access is
ignored.
Table 19.5-1 Command Sequence Table
Bus
Command
Write
Sequence
Access
Read/
1
Reset*
Read/
4
Reset*
Write
4
program
Chip
6
erace
Sector
6
erase
Sector erase suspend
Sector erase resume
RA: Read address
PA: Write address
SA: Sector address (Specify an arbitrary address in sector)
RD: Read data
PD: Write data
U: The upper 4 bit same as RA, PA, SA
*: Both 2 types of read/reset command can reset flash memory to read mode.
Notes:
• Addresses in the table are the values in the CPU memory map. All addresses and data are hexadecimal
values, where "x" is any value.
• The address representations "U" in the table are not arbitrary; the four address bits (bits 15 to 12) must
have the same value as RA, PA, and SA.
Example:
When RA = FFC48EH -> U = C
When SA = FF3000H -> U = 3
When PA = FF1024H -> U = 1
• The chip erase command is accepted only when all sectors have been write-enabled. The chip erase
command is ignored when any of the sector write-enable/protect bits in the flash memory write control
register (FWR0/1) contains "0" (write-protected or accidental write prevented status).
Write Cycle of
Write Cycle of
First Bus
Second Bus
Address Data
Address
Data
FFXXXX
XXF0
-
-
H
H
FFUAAA
XXAA
FFU554
XX55
H
H
H
FFUAAA
XXAA
FFU554
XX55
H
H
H
FFXAAA
XXAA
FFX554
XX55
H
H
H
FFUAAA
XXAA
FFU554
XX55
H
H
H
Input address"FFXXXX
Input address"FFXXXX
CHAPTER 19 512 KBIT FLASH MEMORY
Write Cycle of
Write Cycle of
Third Bus
Fourth Bus
Address
Data
Address
Data
-
-
-
FFUAAA
XXF0
RA
RD
H
H
H
FFUAAA
XXA0
PA
PD
H
H
H
FFXAAA
XX80
FFXAAA
XXAA
H
H
H
H
FFUAAA
XX80
FFUAAA
XXAA
H
H
H
H
" Data (xxB0
) suspends sector erasing.
H
H
" Data (xx30
) suspends and resume sector erasing.
H
H
Write Cycle of
Write Cycle of
Fifth Bus
Sixth Bus
Address
Data
Address
-
-
-
-
-
-
-
-
-
-
FFX554
XX55
FFXAAA
H
H
H
H
SA
FFU554
XX55
H
H
H
Data
-
-
-
XX10
H
XX30
H
587
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