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I Notes on Reset Factor Bit
G
Power on reset
When a power on reset is executed, the PONR bit is set to "1" after completion of the reset operation. Any
reset factor bit other than the PONR bit is undefined. When the PONR bit is "1" after completion of the
reset operation, ignore the value of any bit other than the PONR bit.
G
At two or more reset factors
The reset factor bit is set to "1" according to each reset factor even when two or more reset factors are
generated. For example, if the watchdog timer overflows and an external reset request is generated from the
RST pin at the same time, both WRST and ERST bits are set to "1" after completion of the reset operation.
G
Clearing of reset factor bit
Once set, the reset factor bit is not cleared even if any reset factor other than the set factor is generated. The
reset factor bit is cleared after the completion of reading the watchdog timer control register (WDTC).
Reference:
For details on the watchdog timer, see CHAPTER 6 Watchdog timer.
CHAPTER 3 CPU
105
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